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1 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl april 2004 2004 integrated device technology, inc. dsc 6196/6 c IDT8535-01 commercial and industrial temperature ranges low skew, 1-to-4 lvcmos-to-3.3v lvpecl fanout buffer the idt logo is a registered trademark of integrated device technology, inc. features: ? four differential 3.3v lvpecl outputs ? selectable clk0 or clk1 inputs for redundant and multiple frequency fanout applications ? maximum output frequency: 266mhz ? clk0 or clk1 can accept lvcmos or lvttl input levels ? translates lvcmos and lvttl levels to 3.3v lvpecl levels ? output skew: 30ps (max.) ? part-to-part skew: as low as 150ps ? propagation delay: 1.9ns (max.) ? 3.3v operating supply ? available in tssop package description: the IDT8535-01 is a low skew, high performance 1-to-4 lvcmos-to-3.3v lvpecl fanout buffer. it has two single-ended clock inputs. the single-ended clock input accepts lvcmos or lvttl input levels and translates them to 3.3v lvpecl levels. the clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the idt8535- 01 ideal for those applications demanding well-defined performance and repeatability. functional block diagram clk_en clk0 clk1 clk_sel 0 1 d le q q0 xq0 q1 xq1 q2 xq2 q3 xq3
2 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl pin configuration note: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. absolute maximum ratings (1) symbol description max unit v dd power supply voltage 4.6 v v i input voltage ?0.5 to v dd +0.5 v v o output voltage ?0.5 to v dd +0.5 v ja package thermal impedance (0 lfpm) 92.6 c/w t stg storage temperature ?65 to +150 c capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description typ. max. unit c in input capacitance ? 4 pf r pullup input pullup resistor 51 ? k ? r pulldown input pulldown resistor 51 ? k ? tssop top view 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v ee clk_en clk_sel clk0 nc clk1 nc nc nc v dd q0 xq0 v dd q1 xq1 q2 xq2 v dd q3 xq3 pin description (1) symbol number type description v ee 1 pwr negative supply pin clk_en 2 input pullup synch ronizing clock enable. when high, clock outputs follow clock input. when low, q outputs are forced low, xq outputs are forced high. lvcmos / lvttl interface levels. clk_sel 3 input pulldown clock select input. when high, selects clk1 input. when low, selects clk0 input. lvcmos / lvttl interface levels. clk0 4 input pulldown lvcmos / lvttl clock input clk1 6 input pulldown lvcmos / lvttl clock input n c 5, 7, 8, 9 unused no connection v dd 10, 13, 18 power positive supply pins xq3, q3 11, 12 output differential output pair. lvpecl interface levels. xq2 q2 14, 15 output differential output pair. lvpecl interface levels. xq1, q1 16, 17 output differential output pair. lvpecl interface levels. xq0, q0 19, 20 output differential output pair. lvpecl interface levels. note: 1. pullup and pulldown refer to internal input resistors. see capacitance table for typical values.
3 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl control input function table (1,2) inputs outputs clk_en clk_sel selected source q0 to q3 xq0 to xq3 0 0 clk0 disab led; low disabled; high 0 1 clk1 disab led; low disabled; high 1 0 clk0 enabled enabled 1 1 clk1 enabled enabled notes: 1. after clk_en switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the clk_en timing diagram below. 2. in active mode, the state of the outputs is a function of the clk / xclk and pclk / xpclk inputs as described in the clock in put function table. clock input function table (1) inputs outputs clk0 or clk1 q0 to q3 xq0 to xq3 0lh 1hl note: 1. h = high l = low clk en clk0, clk1 xq0, xq1, xq2, xq3 disabled enabled q0, q1, q2, q3 clk_en timing diagram
4 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl notes: 1. measured from the v dd /2 of the input to the differential output crossingpoint. 2. defined as skew between outputs as the same supply voltage and with equal load conditions. measured at the output differenti al crosspoints 3. defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. u sing the same type of inputs on each device, the outputs are measured at the differential crosspoints. 4. this parameter is defined in accordance with jedec standard 65. ac electrical characteristics - commercial all parameters measured at 266mhz unless noted otherwise; cycle-to-cycle jitter on input = jitter on output; the part does not add jitter symbol parameter test conditions min. typ. max. unit f max output frequency 266 m h z t pd propagation delay (1) f 266mhz 1 1.9 ns t sk ( o ) output skew (2,4) 11 30 ps t sk ( pp ) part-to-part skew (3,4) 150 ps t r output rise time 20 - 80% @ 50mhz 300 700 ps t f output fall time 20 - 80% @ 50mhz 300 700 ps odc output duty cycle 48 50 52 % power supply characteristics - commercial symbol parameter test conditions min. typ. max. unit v dd positive supply voltage 3.135 3.3 3.465 v i ee power supply current ? ? 50 ma note: 1. outputs terminated with 50 ? to v dd - 2v. dc electrical characteristics, lvpecl - commercial symbol parameter test conditions min. typ. max. unit v oh output voltage high (1) v dd - 1.4 v dd - 1 v v ol output voltage low (1) v dd - 2 v dd - 1.7 v v swing peak-to-peak output voltage swing 0.6 0.85 v dc electrical characteristics, lvcmos / lvttl - commercial symbol parameter test conditions min. typ. max. unit v ih input voltage high 2 v dd + 0.3 v v il input voltage low clk0, clk1 -0.3 1.3 v clk_en, clk_sel -0.3 0.8 i ih input current high clk0, clk1, clk_sel v in = v dd = 3.465v 150 a clk_en v in = v dd = 3.465v 5 i il input current low clk0, clk1, clk_sel v in = 0v, v dd = 3.465v -5 a clk_en v in = 0v, v dd = 3.465v -150
5 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl notes: 1. measured from the v dd /2 of the input to the differential output crossingpoint. 2. defined as skew between outputs as the same supply voltage and with equal load conditions. measured at the output differenti al crosspoints 3. defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. u sing the same type of inputs on each device, the outputs are measured at the differential crosspoints. 4. this parameter is defined in accordance with jedec standard 65. ac electrical characteristics - industrial all parameters measured at 266mhz unless noted otherwise; cycle-to-cycle jitter on input = jitter on output; the part does not add jitter symbol parameter test conditions min. typ. max. unit f max output frequency 266 m h z t pd propagation delay (1) f 266mhz 1 1.9 ns t sk ( o ) output skew (2,4) 30 ps t sk ( pp ) part-to-part skew (3,4) 200 ps t r output rise time 20 - 80% @ 50mhz 300 700 ps t f output fall time 20 - 80% @ 50mhz 300 700 ps odc output duty cycle 48 50 52 % power supply characteristics - industrial symbol parameter test conditions min. typ. max. unit v dd positive supply voltage 3.135 3.3 3.465 v i ee power supply current ? ? 55 ma note: 1. outputs terminated with 50 ? to v dd - 2v. dc electrical characteristics, lvpecl - industrial symbol parameter test conditions min. typ. max. unit v oh output voltage high (1) v dd - 1.4 v dd - 1 v v ol output voltage low (1) v dd - 2 v dd - 1.7 v v swing peak-to-peak output voltage swing 0.6 0.85 v dc electrical characteristics, lvcmos / lvttl - industrial symbol parameter test conditions min. typ. max. unit v ih input voltage high 2 v dd + 0.3 v v il input voltage low clk0, clk1 -0.3 1.3 v clk_en, clk_sel -0.3 0.8 i ih input current high clk0, clk1, clk_sel v in = v dd = 3.465v 150 a clk_en v in = v dd = 3.465v 5 i il input current low clk0, clk1, clk_sel v in = 0v, v dd = 3.465v -5 a clk_en v in = 0v, v dd = 3.465v -150
6 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl part-to-part skew lvpecl 50 ? 50 ? z = 50 ? v dd v ee = -1.3v 0.135v v dd = 2v z = 50 ? qx xqx scope xqx qx xqy qy t sk(0) xqx qx xqy qy t sk(pp) part 1 part 2 parameter measurement information output skew output load test circuit
7 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl v swing t r t f 20% 80% 80% 20% clock outputs clk0, clk1 xq0, xq1, xq2, xq3 q0, q1, q2, q3 t pd xq0, xq1, xq2, xq3 q0, q1, q2, q3 odc = t w t period pulse width t period odc and t period propagation delay output rise and fall time parameter measurement information - continued
8 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl application information termination for lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are rec ommended only as guidelines. f out and xf out are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. the diagrams below show two different layouts which ar e recommended only as guidelines. other suitable clock layouts may exist. it is recommended that the board designers simulate to guarantee compatib ility across all printed circuit and clock component process variations. lvpecl output termination, layout a lvpecl output termination, layout b f out 50 ? 50 ? zo = 50 ? v dd - 2v zo = 50 ? r tt f in r tt = (v oh + v ol / v dd - 2) - 2 1 zo f out zo = 50 ? zo = 50 ? f in zo 3 2 zo 3 2 zo 5 2 zo 5 2 3.3v
9 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl power considerations this section provides information on power dissipation and junction temperature for the IDT8535-01. equations and example calc ulations are also provided. power dissipation: the total power dissipation for the IDT8535-01 is the sum of the core power plus the power dissipated in the load(s). the foll owing is the power dissipation for the v dd = 3.3v + 5% = 3.465v, which gives worst case results. please refer to the following section, calculations and equations , for details on calculating power dissipated in the load. power (core) max = v dd _ max * i cc _ max = 3.465 * 50ma = 173.25mw power (outputs) max = 30.2mw/loaded output pair if all outputs are loaded, the total power is 4 * 30.2mw = 120.8mw total power_ max (3.465v, with all outputs switching) = 173.25mw + 120.8mw = 294.05mw junction temperature: junction temperature (t j ) is the temperature at the junction of the bond wire and bond pad. it directly affects the reliability of the device. the ma ximum recommended junction temperature for this device is 125c. the equation for is as follows: t j = ja * pd_total + t a t j = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in power dissipation , above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ( ja ) must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 77.6c/w per the following thermal resistance table. therefore, t j for an ambient temperature of 70c with all its outputs switching is: 70c + 0.294w * 77.6c/w = 92.81c. this is well below the limit of 125c. this calculation is only an example. t j will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single- layer or multi-layer). thermal resistance ja for 20-pin tssop, forced convenction ja by velocity (linear feet per minute) 0 200 400 unit multi-layer pcb, jedec standard test boards 92.6 77.6 70.9 c/w
10 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl calculations and equations v dd q1 v out rl 50 v dd - 2v lvpecl output driver circuit and termination to calculate worst case power dissipation into the load, use the following equations, which assume a 50 ? load and a termination voltage of v dd ? 2v. for logic high: v out = v oh _ max = v dd _ max ? 1v. (v dd _ max ? v oh _ max ) = 1v for logic low: v out = v ol _ max = v dd _ max ? 1.7v. (v dd _ max ? v ol _ max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is power dissipation when the output drives low. pd_h = {[ v oh _ max ? (v dd _ max ? 2v)] / r l } * (v dd _ max ? v oh _ max ) = {[ 2v ? (v dd _ max ? v oh _ max )] / r l } * (v dd _ max ? v oh _ max ) = [( 2v ? 1v) / 50 ? ] * 1v = 20mw. pd_l = {[ v ol _ max ? (v dd _ max ? 2v)] / r l } * (v dd _ max ? v ol _ max ) = {[ 2v ? (v dd _ max ? v ol _ max )] / r l } * (v dd _ max ? v ol _ max ) = [( 2v ? 1.7v) / 50 ? ] * 1.7v = 10.2mw. total power dissipation per output pair = pd_h + pd_l = 30.2mw
11 commercial and industrial temperature ranges IDT8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xxxxx xx x package process device type blank i 8535-01 low skew, 1-to-4 lvcmos-to-3.3v lvpecl fanout buffer thin shrink small outline package pg commercial (0c to +70c) industrial (-40c to +85c)

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